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Physical Design Lead(High Speed IP's)

AMD
Bengaluru, IND
Full-time
Lead · 10+ years experience
Discovered 4 days ago
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Free

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TECHNICAL SKILLS

  • Physical Design and Signoff
  • STA and Timing Closure
  • Clock Architecture and CTS
  • Floorplanning and Power Planning
  • IR/EM Analysis
  • Physical Verification
  • SI/PI Analysis
  • Low Power Design (UPF/CPF)
  • Advanced Node Design Methodologies
  • Tcl/Python/Scripting
  • AI-assisted Design Flows (preferred)
  • LEADERSHIP EXPECTATIONS
  • Leads strategic technical initiatives across multiple IP programs.
  • Mentors and develops engineering talent.
  • Drives innovation that improves product competitiveness, engineering productivity, and design quality.
  • EDUCATION
  • BS/MS in Electrical Engineering, Computer Engineering, VLSI Design, or related field.
  • #LI-PM2
  • Benefits offered are described: AMD benefits at a glance.
  • AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
  • AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
  • This posting is for an existing vacancy.

Qualifications

  • Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

  • SMTS SILICON DESIGN ENGINEER THE ROLE AMD is looking for an experienced and highly motivated Member of Technical Staff (MTS) to join the CT Physical Design team. In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products. As a technical leader, you will work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC, and methodology teams to define and implement innovative physical design solutions that achieve aggressive PPA, frequency, power, and schedule goals on advanced process nodes. The ideal candidate combines deep physical design expertise with strong leadership capabilities and a proven track record of delivering complex, high-performance IPs to production. THE PERSON You are passionate about solving complex physical design challenges in advanced semiconductor technologies. You thrive in fast-paced environments, influence technical direction beyond your immediate team, and enjoy mentoring engineers while driving innovation in implementation methodologies. You possess deep understanding of high-speed digital and mixed-signal design implementation and have successfully delivered multiple tape-outs in advanced technology nodes. KEY RESPONSIBILITIES - Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems. - Own end-to-end implementation activities including some or all of these domains: - Floorplanning - Power planning - Placement - Clock architecture - CTS - Timing closure - Signal integrity closure - Physical verification

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