Physical Design / Implementation Lead

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

We're hiring the first permanent Physical Design / Implementation Lead for the digital design team. This is a build role: you'll be responsible for all aspects of the SoC implementation process. Responsibilities include building and managing a multi-site team to deliver optimized GDSII implementations on subsystem and SoC levels across a variety of planar, FinFet and GAA technologies. You will define how we take designs from RTL to tapeout on leading-edge nodes, and grow the team under you. You'll be one of three discipline leads, alongside RTL and DV, who together own how digital chips get built at Neurophos.