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The Electronic IC (EIC) is the high-speed mixed-signal ASIC at the heart of our optical compute engine. It drives, reads out, and controls our photonic hardware and connects it to the rest of the system. We are looking for an experienced hardware TPM to drive the EIC program end-to-end: from architecture convergence with our chip architects, through design, verification, physical design, and tapeout at a leading-edge foundry, into post-silicon bring-up and system integration.
You will be the connective tissue between the architecture team, digital/analog/mixed-signal design, DV, physical design, packaging, photonics, and platform hardware — and the single source of truth for EIC schedule, risk, and readiness. This is a first-silicon program at a fast-moving startup: you will define the process where none exists, and you'll be judged on working silicon.
We develop silicon the AI-first way. AI agents and LLM tooling are embedded in how we write specs, track requirements, generate and review code, close verification, and run the program itself. You'll drive it: building an AI-augmented program machine.
The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
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Join us and shape the future of computing!
The Electronic IC (EIC) is the high-speed mixed-signal ASIC at the heart of our optical compute engine. It drives, reads out, and controls our photonic hardware and connects it to the rest of the system. We are looking for an experienced hardware TPM to drive the EIC program end-to-end: from architecture convergence with our chip architects, through design, verification, physical design, and tapeout at a leading-edge foundry, into post-silicon bring-up and system integration.
You will be the connective tissue between the architecture team, digital/analog/mixed-signal design, DV, physical design, packaging, photonics, and platform hardware — and the single source of truth for EIC schedule, risk, and readiness. This is a first-silicon program at a fast-moving startup: you will define the process where none exists, and you'll be judged on working silicon.
We develop silicon the AI-first way. AI agents and LLM tooling are embedded in how we write specs, track requirements, generate and review code, close verification, and run the program itself. You'll drive it: building an AI-augmented program machine.
Neurophos is a private semiconductor company developing photonic AI inference chips for data centers.
Visit company websiteJobs and hiring trendsUSD 160000-195000 yearly / year
Full-time
Senior · 10+ years experience
Onsite
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