Mixed Signal Design Engineer
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Key skills for this role
About the Role
Ciena is seeking a Mixed Signal Design Engineer to join the Wavelogic team, designing high-speed analog macros for optical fiber transmission. The role involves designing Sigma-Delta DAC/ADC, creating SystemVerilog and IBIS-AMS models, and collaborating with cross-functional teams.
Key Skills for This Role
Responsibilities
- Design high precision Sigma Delta DAC and ADC for control and monitoring
- Design SystemVerilog models for various analog macros
- Design IBIS AMS models for high speed DAC and ADC based SerDes IP running at 56Gbd, 112Gbd, 224Gbd, and 448Gbd
- Create Design Specification Document
- Interact with and provide support to system, analog, digital, DSP, signal integrity, hardware, firmware, and analog lab bring up teams
Requirements
- Electrical or computer engineering, computer science or other applicable scientific degree at BEng/BSc, MEng/MSc, or PhD level
- Design experience in the latest CMOS and BiCMOS technology
- Proficiency with Cadence Virtuoso/Xcelium/AMS, Synopsys VCS/StarRC, Siemens Questa/Formal/Calibre/SymphonyAMS/AFS
- Familiarity with SystemVerilog, VerilogAMS, VerilogA, Matlab/Simulink, C/C++, Python languages
- Ability to work independently and collaboratively with team members
- Skills of writing and presenting in English
Full Job Posting
How You Will Contribute
- The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions.
- Successful candidates will join a vibrant team with a proven track record over 30 years in high speed circuits for broadband fiber optic modems.
- This team pioneered the world's first high speed DAC and ADC analog macros for coherent fiber optic product solutions.
- Reporting to the Senior Manager of Analog Engineering.
Responsibilities
- Designing the high precision Sigma Delta DAC and ADC for control and monitoring
- Designing the SystemVerilog models for various analog macros
- Designing the IBIS AMS models for the high speed DAC and ADC based SerDes IP running at 56Gbd, 112Gbd, 224Gbd, and 448Gbd
- Creating Design Specification Document
- Interacting with and providing support to the system team, analog team, the digital team, the DSP team, the signal integrity team, the hardware team, firmware team, and the analog lab bring up team
The Must Haves
- Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc, MEng/MSc, or PhD level
- Design experience in the latest CMOS and BiCMOS technology
- Proficiency with Cadence Virtuoso/Xcelium/AMS, Synopsys VCS/StarRC, Siemens Questa/Formal/Calibre/SymphonyAMS/AFS
- Familiarity with SystemVerilog, VerilogAMS, VerilogA, Matlab/Simulink, C/C++, Python languages
- Ability to work independently and collaboratively with team members
- Skills of writing and presenting in English
Assets
- Knowledge of UVM, Git, Gradle, Google Tests
- Experience with the RF and Signal Integrity tools
- DSP, digital, and analog design and modelling in high SerDes application
- AI tools for automation
Pay Range
- The annual salary range for this position is CAD 90,600 CAD 144,800 CAD.
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