Memory Layout Design Engineer

Job Requirements:

Minimum 8+ years of experience with a Bachelor's degree or 6+ years of experience with a Master's degree, strong layout knowledge.

Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).

Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.

Key Responsibilities:

Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.

Manage scheduling, timelines, and layout floor-planning.

Ensure end-to-end deliverables are completed with high quality and within the planned schedule.

Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.

Skill Set(Memory):

Proven ability to manage schedules, timelines, and end-to-end deliverables.

Experienced in leading teams, training junior engineers, and documenting layout methodologies and guidelines.

Proficient in Cadence tools, including Virtuoso Layout, Layout XL, VXL, EXL, and Cadence Schematic Capture.

Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.

Extensive experience with physical verification tools such as Calibre and Hercules (DRC, LVS, ERC, Antenna, and Softcheck Errors).

Proficiency in floor-planning, hierarchy layout, and chip integration.

Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.

Ability to lead teams, train junior engineers, and manage projects effectively.

Strong knowledge of memory layout topology; experience with memory compilers is preferred.

Knowledge of AI, layout automation, and script/SKILL programming is preferred.