Machine Learning Performance Engineer (Inference)

• Analyze and enhance execution across deep memory hierarchies to maximize resource utilization and parallel processing. You will assess and resolve memory subsystem and interconnect bottlenecks across the end-to-end inference lifecycle.

• Collaborate with Infrastructure teams to understand thermal, power, and operational constraints of hardware platforms to design inference strategies for our latency-critical trading strategies that fit within those envelopes.

• Develop highly optimized kernels and integrate specialized performance libraries to extract maximum computational throughput from the underlying silicon.

• Implement advanced model reduction techniques (quantization, pruning, distillation) to ensure compact memory footprints and numerical stability. Prioritize optimization for low-latency, event-level inference workloads to meet real-time trading requirements.
• Cross-Functional Collaboration:
• Collaborate closely with ML Researchers, HPC Engineers, FPGA Engineers, and Datacenter Engineers to bring to fruition target deployments.

• 2+ years of experience optimizing deep learning inference in latency-sensitive or high-throughput production environments, in any domain.
• ML Frameworks: Deep expertise in lower-level ML framework development (PyTorch/JAX), paired with strong Python/C++ skills and a thorough understanding of mixed-precision computation.
• Kernel Development & Optimization Tooling: Proven experience in custom GPU kernel development. Deep familiarity with advanced optimization libraries and compilers (e.g., Triton, TensorRT, ONNX, IREE, HLS4ML, cuBLAS, CUTLASS) as well as profiling tools (e.g., Nsight Systems, Nsight Compute).
• GPU Architecture Mastery: Deep expertise in GPU microarchitecture, encompassing SM execution, warp scheduling, and full memory hierarchy optimization (registers to HBM).
• Cross-Architecture Benchmarking: Proven record of rigorous, data-driven approach to evaluating inference performance across heterogeneous compute architectures.
• Bonus: Practical experience targeting and optimizing inference workloads on specialized hardware ecosystems, including FPGAs and ASICs.
• Prior experience in financial trading is not required.

Anticipated annual base salary range $200,000-$300,000, plus eligible for discretionary bonus.

Tower’s headquarters are in the historic Equitable Building, right in the heart of NYC’s Financial District and our impact is global, with over a dozen offices around the world.

At Tower, we believe work should be both challenging and enjoyable.

That is why we foster a culture where smart, driven people thrive – without the egos.

Our open concept workplace, casual dress code, and well-stocked kitchens reflect the value we place on a friendly, collaborative environment where everyone is respected, and great ideas win.

Our benefits include:

• Generous paid time off policies
• Savings plans and other financial wellness tools available in each region
• Hybrid working opportunities
• Free breakfast, lunch, and snacks daily
• In-office wellness experiences and reimbursement for select wellness expenses (e.g., gym, personal training and more)
• Company-sponsored sports teams and fitness events (JPM Corporate Challenge, Cycle for Survival, Wall Street Rides FAR and more)
• Volunteer opportunities and charitable giving
• Social events, happy hours, treats, and celebrations throughout the year
• Workshops and continuous learning opportunities

At Tower, you’ll find a collaborative and welcoming culture, a diverse team and a workplace that values both performance and enjoyment.

No unnecessary hierarchy.

No ego.

Just great people doing great work – together.

Tower Research Capital is an equal opportunity employer.