Lead Systems/DSP Engineer

We are seeking a seasoned DSP / System Architect to lead the design of next-generation high-speed (25G+) physical layer (PHY) .

In this role, you will define and drive the end-to-end DSP architecture , from system-level modeling through silicon validation, enabling highly optimized, low-power, and high-performance transceiver implementations.

This is a high-impact technical leadership role at the intersection of signal processing, mixed-signal design, and system architecture.

You will work closely with cross-functional teams to translate advanced algorithms into robust, production-ready silicon.

• Define and own the DSP/system architecture for high-speed transceivers , balancing power, performance, and silicon area
• Drive key architectural decisions across DSP, analog front-end, and system partitioning
• Lead system-level trade-offs and provide technical direction across the organization

• Develop and maintain high-fidelity system models of complete transceivers using MATLAB, Simulink, Python, and/or C++
• Design, evaluate, and optimize advanced equalization techniques, including FFE, DFE and MLSD
• Architect robust Clock and Data Recovery (CDR) solutions with wide frequency acquisition range and very low phase noise
• Develop efficient and advance echo cancellation algorithms for full-duplex high-speed links optimizing for power and silicon area
• Design adaptive DSP algorithms with strong focus on rate of convergence, robustness, and implementation efficiency
• Develop channel model including nonlinear effects and complex noise sources

• Translate system-level requirements into block-level specifications (AFE, ADC/DAC, PLL, DSP blocks, etc.)
• Collaborate closely with analog, RTL, and physical design teams to ensure accurate and efficient implementation
• Ensure alignment between algorithm models and hardware realization

• Drive pre-silicon to post-silicon correlation, ensuring models accurately predict silicon behavior
• Define and support silicon bring-up, characterization, and debugging
• Establish lab validation methodologies and support compliance testing and performance benchmarking
• Contribute to system-level bring-up and production ramp readiness

• MS or PhD in Electrical Engineering or a related discipline
• 10+ years of experience in DSP/system architecture for high-speed communication systems
• Deep expertise in digital communications theory including advanced, efficient and adaptive equalization and echo cancellation algorithms, CDR algorithms, phase noise characterization and loop dynamic analysis, channel modeling and nonlinear effects
• Strong hands-on experience with system modeling tools ( MATLAB, Simulink, Python, C++ )
• Solid understanding of mixed-signal design fundamentals , including ADC/DAC architectures, PLL behavior and phase noise analysis, channel and analog front-end modeling including non-idealities
• Proven track record of driving complex systems from concept to silicon

• Experience in designing high-speed IEEE 802.3 transceivers for automotive, robotics and data center applications over both optical and copper channels
• Prior technical leadership or mentoring experience

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $180,000 - $250,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

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