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Lead RTL Design Engineer
Cerebras Systems
Sunnyvale, USA
Full-time
Senior · 8+ years experience
Hybrid
USD 175000-275000 yearly / year
Discovered 1 weeks ago
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Role Overview
As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).
This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.
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About The Role
As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).
This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.
Responsibilities
- Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
- Managing external ASIC vendor through product development cycle.
- Work closely with PD team members for design closure to meet PPA goals.
- Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
- Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
- Debug silicon-level functional, timing, and power issues during bring up.
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