greenhouse
Lead DFT Engineer (Edge Computing)
EnCharge AI
IND
Full-time
Senior · 12+ years experience
Onsite
Discovered 3 weeks ago
Synopsys TestMAXSiemens/Mentor TessentCadence ModusMBISTIJTAG (IEEE 1687)Boundary scan (IEEE 1149.1/6)
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Synopsys TestMAXSiemens/Mentor TessentCadence Modus
Role Overview
Lead DFT Engineer (Edge Computing) Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.
As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.
Key Skills for This Role
Synopsys TestMAXSiemens/Mentor TessentCadence ModusMBISTIJTAG (IEEE 1687)Boundary scan (IEEE 1149.1/6)
Full Job Posting
Key Responsibilities
- Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.
- Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
- Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST.
- Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis .
- Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.
Technical Requirements
- Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role.
- Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).
- Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN , IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).
- Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).
- Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.
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