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Lead Camera Electronics Engineer (Embedded Systems)
GalaxEye
Bengaluru, IND
Full-time
Senior · 6+ years experience
Onsite
Discovered 3 weeks ago
DDR3/DDR4LVDS/CMLSerDesRTOSQSPI/NANDDFM/DFT
Free
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Ready to ScanKey skills for this role
DDR3/DDR4LVDS/CMLSerDes
Key Skills for This Role
DDR3/DDR4LVDS/CMLSerDesRTOSQSPI/NANDDFM/DFT
Full Job Posting
- Define robust CE architecture, ICDs, dataflow, clocks/resets, power domains, fault handling, safe-mode hooks.
- Trade studies for FPGA/SoC choice, storage, and high-speed links.
- Lead schematic + PCB design (high-speed + mixed-signal), DFM/DFT, EMI/EMC practices, grounding/fusing, thermal conduction design (space/vacuum context).
- Interfaces: DDR3/DDR4 (SI closure), NVMe/SATA SSD (PCIe Gen4 x4+), SerDes transceivers (GTX/GTH/GTY/GTM), LVDS/CML.
- Own sensor/ROIC electrical interface spec, timing budgets, exposure/control loops, register maps.
- Hands-on with modern sensor links (e.g., SLVS-EC / sub-LVDS / LVDS ) and/or industrial vision links (Camera Link / CoaXPress / GigE Vision / USB3 Vision).
- If ROIC is external/custom: drive requirements, review design/verification with ASIC partner, and own validation plan (bench → thermal → radiation strategy). (Modern ROICs often push very high-speed serial links—design must anticipate this.)
- Architect high-throughput RTL (DMA, DFX, buffering, packetization, compression hooks) and timing closure.
- Boot chain (FSBL/U-Boot), QSPI/NAND, Linux/RTOS drivers, board support, and production-ready images.
- Hardware–firmware co-design: clean register maps, test hooks, driver APIs, HIL automation.
- SI validation (DDR + SerDes): eye diagrams, BER, link margining; lab instrumentation strategy.
- Test-as-you-fly mindset: unit tests, stress tests, long-duration soak, and environmental test support.
- Lead a team of engineers to achieve the above milestones.
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6 years in embedded hardware + FPGA/SoC systems shipping real high-speed products.
- Deep hands-on with DDR3/DDR4 , PCIe (Gen3/Gen4) , high-speed transceivers, and board bring-up.
- Strong FPGA/SoC experience: Xilinx/AMD Zynq UltraScale+ and/or Versal (preferred).
- Fundamental knowledge of Real time operating system (RTOS) or Bare metal coding.
- Proven ownership: architecture → implementation → debug → validation → release.
- Comfortable leading a small team and driving cross-functional execution (systems, sensor, optics, software).
- Space-grade design practices: radiation mitigation (TID/SEE strategy), de-rating, watchdog/fault tolerance.
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