Layout Design Intern (Fall 2026)

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era.

We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration.

Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job.

Connect with a career that matters.

• Contribute to layout feasibility studies in partnership with senior analog designers, evaluating design trade-offs and layout strategies for high-speed circuits
• Develop custom layouts for advanced analog and mixed-signal blocks, following structured methodologies for floorplanning, placement, and routing
• Execute comprehensive physical verification, including design rule checks (DRC), layout versus schematic (LVS), electromigration (EM), and infrared (IR) drop analysis to ensure layout quality and reliability
• Explore new layout tool features, flows, and processes to enhance efficiency and productivity
• Collaborate closely with circuit designers and layout engineers to identify and resolve layout-related risks early in the design cycle
• Provide clear status updates and participate in team meetings, design discussions, and knowledge-sharing activities
• Education: Actively enrolled in a degree program in Electrical Engineering or a related field,
• Hands-on experience with custom analog and mixed-signal layout design in deep sub-micron complementary metal-oxide semiconductor (CMOS) technologies
• Strong understanding of layout techniques, including floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerations
• Experience creating custom layouts for analog or mixed-signal blocks such as operational amplifiers or current mirrors
• Familiarity with semiconductor manufacturing processes and foundry design rules
• Experience using industry-standard layout tools such as Cadence Virtuoso and Siemens Calibre
• Ability to interpret and debug DRC and LVS reports effectively
• Exposure to high-speed data converter or phase-locked loop (PLL) layout design
• Familiarity with bipolar CMOS (BiCMOS) technologies
• Scripting experience using PERL or SKILL to support layout automation or productivity improvements