IP RTL Senior Design Engineer

As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified Intel Chassis designs. This position is at the forefront of Intel's innovation, ensuring that our products consistently deliver world-class performance, power efficiency, and reliability. Work closely with architects to define and design complex protocol bridges. Define and implement range-based access control for secured memory and register paths across HBW and LBW. Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths. Design and validate parity/ECC generation and checking for request, response, and data channels. Define fault behavior for unauthorized accesses and corrupt transactions, including silent block semantics, RAZWI-style handling, poison propagation, and timeout cleanup. Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling. Support error injection, diagnostics, and post-silicon debug hooks for both security and reliability validation. Define and implement telemetry capture for fabric load, latency, congestion, error context, and other operational health indicators. Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure. Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical. Integrate trigger, monitor, and logging hooks needed for bring-up, stress triage, and post-silicon correlation. Work with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are useful, stable, and diagnosable. Balance observability depth against area, timing, bandwidth, and survivability constraints. Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features. Key Responsibilities:

Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.

Define architecture and microarchitecture features for the IP block being designed.

Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.

Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.