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IP RTL Design Engineer
Intel
Bengaluru, IND
Full-time
Senior · 6+ years experience
Onsite
Discovered 1 weeks ago
VerilogVHDLSynthesisTiming analysisFormal verification
Free
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VerilogVHDLSynthesis
Role Overview
Role and Impact:
As a Component IP RTL Design Engineer for Intel Unified Chassis, you will be responsible for developing, implementing, and supporting a variety of IP components, with a major focus on protocol bridges.
In this role, you will collaborate with architects and senior engineers to define, design, and validate protocol bridge solutions, as well as other IP blocks as required for Unified Intel Chassis designs.
Your primary work will involve protocol conversion, access control, and error handling across interfaces such as AXI, AXI-Lite, APB, IOSF-SB, HBW, and LBW, but you may also contribute to other IP development, integration, and debug activities to meet system-level requirements and quality standards.
Key Skills for This Role
VerilogVHDLSynthesisTiming analysisFormal verification
Full Job Posting
Role and Impact
As a Component IP RTL Design Engineer for Intel Unified Chassis, you will be responsible for developing, implementing, and supporting a variety of IP components, with a major focus on protocol bridges. In this role, you will collaborate with architects and senior engineers to define, design, and validate protocol bridge solutions, as well as other IP blocks as required for Unified Intel Chassis designs. Your primary work will involve protocol conversion, access control, and error handling across interfaces such as AXI, AXI-Lite, APB, IOSF-SB, HBW, and LBW, but you may also contribute to other IP development, integration, and debug activities to meet system-level requirements and quality standards. Key Responsibilities:
Design, implement, and verify protocol bridges between different bus and interconnect standards (e.g., AXI, AXI-Lite, APB, IOSF-SB, HBW, LBW).
Contribute to the development and support of other IP components as needed for Intel Chassis projects.
Collaborate with architects and senior engineers to define microarchitecture and interface requirements for protocol bridges and other IP blocks.
Develop RTL code and simulations for protocol bridge logic and other IP, ensuring functional correctness and performance targets.
Implement access control, privilege qualification, and policy propagation for secure data paths.
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