Intern - DRAM Test Structure Design and Layout Engineering

• Coursework or project experience in VLSI build, semiconductor processing, or device physics.
• Experience with EDA tools such as Cadence Virtuoso, Calibre, or equivalent.
• Hands-on experience editing semiconductor layout using EDA tools, including crafting, modifying, and reviewing layout data for design-rule compliance.
• Understanding of physical build verification concepts including DRC and LVS.
• Experience with data analysis and visualization tools.

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