High Level Synthesis Compiler Engineer

Job Description:

Responsibilities

• Develop and optimize our compiler for the FPGA design flow: IR and lowering, analysis and transformation passes, correctness- and QoR-driven optimizations, and scalability (runtime and memory) on large designs
• Work closely with customers to enable what they want to do : understand target applications, workflows, and success criteria; advocate for the capabilities, quality-of-results, and turnaround time they need; and turn that into concrete compiler and flow improvements—not only reactive support.
• Mentor talented engineers through code reviews, design reviews, and technical coaching; help grow ownership, design judgment, and execution quality across the team.
• Document and explain behavior, limitations, and workarounds for internal and external audiences where appropriate.
• Stay current with EDA and compiler technology (including LLVM/MLIR ecosystems where applicable), FPGA design practices, and relevant standards.
• Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success. ​