GPU Core Pipeline IP Verification Engineer

As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.

You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.

You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.

You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

Work with HW architects and designers to make the right implementation choices.

You will be working with architects, designers, and other members of your verification teams to accomplish your tasks.

B.Tech./ M.Tech. with 1+ years of relevant experience

Familiarity with Verilog, C++ and OOPs concepts.

Hands-on experience in verification at Unit/Sub-system/SOC level.

Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

Good understanding of computer architecture concepts.

Strong technical fundamentals with superior analytical skills and problem-solving skills

Knowledge in SystemVerilog or similar HVL, experience in verification methodologies like UVM/VMM is highly desirable

Exposure to industry standard verification tools for simulation and debug