FPGA Engineer - Systems Team

Systems Engineering bridges the gap between Riverlane and its customers. They act as the primary technical interface for our customers’ engineers to guide them through product integration and help with troubleshooting complex quantum systems. They are key to securing design wins and driving product development.

As an FPGA Engineer, you will configure our Deltaflow Hardware to connect Quantum Computers to provide low-latency, high throughput systems that perform complex operations in a predictable and guaranteed way. You will use your knowledge and expertise to adapt the hardware to an ever-changing quantum control system to support scientists that are running quantum experiments.

This is a fantastic opportunity to join Riverlane’s team, that is developing the world’s most advanced quantum error correcting algorithms. The Riverlane team is a mix of mathematicians, physicists and engineers, working together on a range of exciting and cutting-edge projects.

Host Technical Workshops on Riverlane’s QEC Interface

Evaluate Customers Control System and Data Communication requirements.

Integration On-Site: End-to-End System Deployment:

Writing RTL to adapt to customers control systems and ensure data packets are received correctly.

Work with Riverlane’s Quantum Application Team to design experiments to test the system.

Benchmark and discover hardware latency limitations.

Troubleshooting and Debugging: Managing Customer Issues:

Report issues and help replicate the setup with the QA team in Riverlane.

Writing script to debug and trace faults

Update verification environment and the test vectors based on data gathered from the experiments that were conducted.

Highlight the success, issues and trends on customer’s Quantum Systems

Feedback key features that will be needed to win current and next generation products

Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)

Experience in writing SystemVerilog

Proven professional experience in at least one of the following areas: Implementation of modern classical decoders on FPGA e.g. LDPC, turbo-codes; Implementation of Ethernet and High-Speed Protocols Implementation of customs protocols and standards.

Implementation of modern classical decoders on FPGA e.g. LDPC, turbo-codes;

Implementation of Ethernet and High-Speed Protocols

Implementation of customs protocols and standards.

Proven capability to test, debug and improve UVM Verification Environment.

Good knowledge of Python and C++

Ability to convert product requirements into technical specifications to document and share your work

A curious nature and a passion for learning and continuous improvement

Excellent communication skills, with the ability to work both independently and collaboratively as part of a team

Experience of working on scientific instrumentation

PhD in a relevant subject

Good knowledge of quantum mechanics.

A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme

Equity, so that our team can share in the long-term success of Riverlane

28 days annual leave, plus bank holidays and enhanced family leave

A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities

A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets