Engineer II, Physical Design - Cores

About the Role --

Responsibilities - What you’ll do

• Learn and Execute: Partner with senior engineers to take CPU blocks through the physical design flow, including synthesis, place & route, and timing closure.
• Bridge Architecture and Implementation: Apply your academic knowledge of computer architecture to understand the underlying RTL. Participate in cross-abstraction-layer co-design discussions to see how pipeline stages, datapaths, and control logic translate into physical wires and gates.
• Analyze PPA Trade-offs: Assist in analyzing timing reports, routing congestion, and power metrics to help the team meet aggressive Power, Performance, and Area goals.
• Flow Automation: Write and maintain scripts (Python, Tcl, Bash) to automate physical design workflows, parse reports, and improve team efficiency.
• Collaborate and Grow: Work cross-functionally with RTL, microarchitecture, and methodology teams. Absorb mentorship from world-class engineers to rapidly develop your backend expertise.

Requirements - What you’ll bring

• Experience: 3+ years. We are open to considering new graduates with excellent academic credentials. If you have some work experience with physical design implementation it will be a big plus.
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong Architectural Foundation: A solid academic grasp of computer architecture fundamentals (e.g., RISC instruction sets, processor pipelining, hazards, memory hierarchy, and cache basics).
• Digital Design Knowledge: Strong understanding of digital logic design and the ability to read and understand RTL (Verilog or SystemVerilog).
• VLSI Exposure: Academic coursework, projects, or internship experience related to VLSI design or ASIC flows.
• Scripting Skills: Proficiency in at least one scripting or programming language commonly used in hardware environments (Python, Tcl, Perl, C++, or Bash).
• Growth Mindset: Highly motivated to learn industry-standard EDA tools (Synopsys or Cadence) and eager to understand the "why" behind physical design challenges, not just the "how."

Why join us?