DSP Engineer

Job requirements

• Master of Science in Electrical Engineering with focus on digital signal processing.
• Strong background in communication theory and wideband digitization.
• 7+ years of hands-on FPGA design and development experience for complex digital systems.
• Strong proficiency in synthesizable RTL design.
• Experience with Vivado, Vitis, equivalent toolchains.
• Extensive high speed serial interface design – JESD204B/C, PCIe Gen3/4, Ethernet, Aurora, equivalent SERDES protocols.
• Ability to partition problems and to define block level HW architectures, and extensive knowledge of VHDL.
• Knowledge of real time implementation of complex DSP parallel processing structures.
• Work with System-on-Chip FPGA platforms, including embedded processors, DMA engines, memory-mapped control interfaces, Linux-based software stacks, and hardware/software partitioning.
• Strong lab debugging skills utilizing high speed oscilloscopes, signal generators, spectrum analyzers, logic analyzers, FPGA debug tools.
• Working knowledge of 5G, LTE related wireless PHY layer concepts including OFDM, FFT/iFFT processing, channel coding, synchronization and DFE processing.
• Experience with AMD RFSoC, Zynq Ultrascale+, Versal AI Core, Microchip Polarfire development.
• Experience with ECSS-E-ST-20-40C and ECSS-Q-ST-60 standards.

Job responsibilities

• Research and design of fast and efficient hardware realizable DSP algorithms to implement functions such as filters, equalizers, timing/carrier recover loops, multi-rate structures (Polyphase Filter Banks), FFT processing engines
• Development and utilize models that provide real life stimulus for testing the developed algorithms including phase and gaussian noise, non-linear RF effects, Doppler, multipath and other channel impairments
• Perform simulation, verification, hardware bring-up, lab debugging, timing analysis, and performance validation using FPGA vendor tools and test equipment.
• Collaborate with systems, RF, software, hardware, and test engineering teams to define requirements, interfaces, verification plans, and system integration approaches.
• Design and integrate high-speed serial interfaces including JESD204B/C, PCIe, Ethernet, Aurora, SERDES, DDR memory interfaces, and AXI-based data paths.
• Develop high-performance RTL using VHDL, Verilog, and/or SystemVerilog, with emphasis on timing closure, resource efficiency, scalability, and maintainability.
• Develop and maintain design documentation, interface control documents, verification reports, timing summaries, utilization reports, and reusable IP documentation.

Job benefits

SWISSto12 has successfully established contracts with Intelsat, Inmarsat, Astrum Mobile and ESA for HummingSat as well as contracts for their RF product line in Europe, and the US with prominent partners and customers such as Thales, Lockheed Martin, Northrop Grumman, SES and the ESA.

SWISSto12 is a spin off from the Swiss Federal Institute of Technology in Lausanne (EPFL), is privately owned and backed by prominent Swiss and European Investors.

SWISSto12 is headquartered in Lausanne, Switzerland, and operates a US and European-subsidiariesy in Foster City California.

The company is well funded for its near and mid-term developments and backed by a solid customer revenue stream.