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Key skills for this role
Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
Work closely with Design, Verification, PD, STA, and ATE teams .
Support DFT activities through tapeout and silicon bring-up .
Ideal Profile: Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up .
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Provides end-to-end semiconductor design and engineering services.
Full-time
Senior · 5+ years experience
Onsite
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