DFT Engineer

Generate ATPG patterns for stuck-at, transition, and path delay faults.

Debug test pattern issues during silicon bring-up.

Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Work closely with RTL design, verification, physical implementation, and test engineering teams.

Support silicon characterization and yield improvement activities.

Contribute to overall microcontroller or SoC DFT methodology.

Bachelor’s/master’s in electrical engineering, Microelectronics, or related field.