DFT Engineer

Role Overview

What You Will Do

• Design and implement test access mechanisms, memory BIST, and scan compression.
• Verify and support silicon bring-up of scan ATPG and other DFT features.
• Develop and deploy DFT methodologies for next-generation products.
• Improve DFT methods and collaborate with multifunctional teams to integrate DFT features into chips.
• Travel occasionally and attend late online meetings during critical milestones.

What We Need To See

• BSEE, MSEE, or equivalent experience.
• At least 2 years of experience, preferably in Design for Testability.
• Knowledge of static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design.
• Experience with RTL and gate verification and simulation.
• Familiarity with BIST architecture and JTAG, IEEE 1149.1, or IEEE 1500.
• Strong knowledge of scan ATPG, compression techniques, and memory testing.
• Expert coding skills in industry-standard scripting languages.