DFT Design Engineer

• Strong knowledge and experience in Spyglass DFT, Scan Architecture (SSN Topology), ATPG and various fault models.

• Hands on skills to implement JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry using industry standard tools.

• Hands on experience in DFT verification using Gate Level Simulations with timing annotations.

• Hands on experience in solving DFT problems, simulation failures, ATPG coverage improvements and DRC debug.

• Good understanding of timing constraints and DFT mode timing analysis.

• Proficiency in RTL coding, shell scripting.

• Experience working with post-Silicon/manufacturing teams on ATE, including debugging and resolving issues.