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DFM RET Engineer
Texas Instruments
Dallas, USA
Mid
Discovered 2 weeks ago
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Role Overview
At 28nm and below, photolithography cannot simply print a chip design as drawn but rather optical diffraction causes critical features to print incorrectly, with direct consequences to yield and device performance.
Solving that problem is your job.
As a DFM/OPC Engineer in TI’s Resolution Enhancement Techniques (RET) team within ATD, you are the technical authority responsible for bridging the gap between what designers draw and what the fab can reliably print.
You’ll develop, optimize, and deploy Optical Proximity Correction (OPC) models and Design for Manufacturability (DFM) solutions that ensure every product tapeout can be accurately realized in silicon at 28nm at yield entitlement.
This role sits at the intersection of computational lithography, layout design, and process integration; your work is a prerequisite for every analog product TI ships from LFAB.
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Responsibilities:
- Develop, evaluate, and implement advanced OPC models and recipes for 28nm and equivalent advanced node technologies
- Perform comprehensive DFM analysis on product designs, identifying and mitigating potential manufacturing issues (e.g., hotspots, yield detractors)
- Collaborate with design teams to define DFM guidelines and ensure layout compliance with manufacturing capabilities
- Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance, yield, and process window
- Interface with OPC and lithography engineers to co-optimize layout structures for printability
- Analyze lithography process data and wafer yield data to identify root causes of patterning defects and drive corrective actions
- Evaluate and qualify new OPC/DFM software tools and methodologies
- Develop and maintain automation scripts for OPC/DFM flows
- Contribute to DFM-aware layout methodologies for custom analog IPs
- Mentor junior engineers and contribute to team knowledge sharing
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