workable
Design Verification Engineer
Erbity Private Limited
Pune, IND
Full-time
Senior · 4+ years experience
Onsite
Discovered 3 weeks ago
SystemVerilogUVMVerilogVHDLSynopsys VCSCadence Xcelium
Free
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SystemVerilogUVMVerilog
Key Skills for This Role
SystemVerilogUVMVerilogVHDLSynopsys VCSCadence Xcelium
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Responsibilities
- Develop and execute comprehensive verification plans and testbenches using industry-standard methodologies.
- Implement test cases and automate verification processes to improve efficiency.
- Analyze verification results, identify issues, and collaborate with design teams to resolve defects effectively.
- Maintain verification documentation, including test reports and coverage analysis.
- Participate in design reviews to provide feedback on testability and implementation.
- Ensure compliance with project schedules and quality standards.
Technical Skills
- Strong proficiency with SystemVerilog and UVM verification methodology.
- Solid understanding of digital design concepts and hardware description languages like Verilog or VHDL.
- Experience with simulation and debugging tools such as Synopsys VCS, Cadence Xcelium, or Questa.
- Familiarity with scripting languages like Python or Tcl for automation purposes.
- Good knowledge of verification techniques including constrained-random testing, coverage-driven verification, and assertions.
Qualifications & Experience
- Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or related fields.
- Proven experience as a Design Verification Engineer or similar role in semiconductor or electronics industry.
- Strong problem-solving skills with attention to detail.
- Excellent communication and teamwork abilities.
Benefits
- Private Health Insurance
- Pension Plan
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