Design Verification Engineer Lead

Skills:

• Experience in one or more of the following areas: C-based SoC design verification (DV), firmware verification exposure, scripting knowledge (Perl/Python/AI/ML based DV), DV flow ownership for functional/firmware verification, deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/CPF/UPF based verification, post-silicon verification, etc.
• Thorough knowledge of standard protocols, such as AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, and high-speed interfaces like CSI and Ethernet.
• Work experience in a C-based environment with complex ARM/DSP multi-processor systems, including power-aware simulations, is a significant plus.
• Strong understanding of digital design fundamentals, computer organization and architectures, and bus protocols.
• Excellent debugging skills with Verilog/VHDL designs.
• Good problem-solving skills.
• Experience with Cadence tools (Xcelium/vManager/Formal JG applications/safety simulator) or similar tools/DV flows.
• Proficiency in AMS, CDC digital verification, formal verification, and post-silicon verification, along with familiarity with functional safety and cybersecurity processes, would be advantageous.
• Effective communication skills to interact seamlessly with all stakeholders.
• Must be highly focused and committed to achieving project goals.