Custom SOC IP Verification Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years.

It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.

Today, we’re tapping into the unlimited potential of AI to define the next era of computing.

An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world.

Doing what’s never been done before takes vision, innovation, and the world’s best talent.

As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

Come join the team and see how you can make a lasting impact on the world.

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions!

We are looking for special individuals with desire to deliver innovative products.

Together, we will build the next generation of life changing custom SOCs!

If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be.

This role specifically requires a skilled ASIC Verification Engineer with expertise in fabric and interconnect verification, spanning both IP and SoC integration.

You will play a key role in verifying the correctness, performance, and compliance of on-chip fabrics and interconnect subsystems — from IP bring-up through full chip integration — ensuring robust and high-performance connectivity across complex SoC designs.

This position demands a motivated individual who understands how complex SOCs and IPs are built, has intimate knowledge of client requirements, and comprehends various development cycles.

It requires deep knowledge of SystemVerilog and UVM, along with a solid grasp of ASIC verification methodologies.

What you'll be doing:

• Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement test plans for fabric and interconnect verification of SoCs using UVM-based environments, targeting both IP-level and system-level scenarios.
• Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, network-on-chip (NoC) topologies, and multi-agent SoC integrations.