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ASIC Implementation Engineer PD
Broadcom
San Jose, USA
Full-time
Senior · 8+ years experience
Discovered 1 weeks ago
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Role Overview
Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division.
This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products.
More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.
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Job Description:
Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products. More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.
Responsibilities:
- Own chip floor planning, partition creation, clock tree and delivery of top level partitions
- Resolve physical design issues related to chip integration and assembly
- Manage all cross functional interactions related to top level floorplanning, I/O and bump planning with package team
- Develop and improve floorplan implementation methodologies using both industry and internal tools
- Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specification
- Preferred qualifications:
- Bachelors degree in Electrical Engineering and 8+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
- Or Master's degree in Electrical Engineering and 6+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
- Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc)
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