ASIC Engineer, Implementation
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Key skills for this role
Role Overview
Meta's Infrastructure Silicon team develops custom silicon for AI, augmented reality, and virtual reality infrastructure.
The ASIC Implementation Engineer contributes to physical implementation of complex custom ASICs from RTL through tape-out.
The role spans synthesis, place-and-route, timing closure, and signoff while working with design, architecture, and verification teams.
Key Skills for This Role
Full Job Posting
Role Overview
Meta's Infrastructure Silicon team develops custom silicon for AI, augmented reality, and virtual reality infrastructure.
The ASIC Implementation Engineer contributes to physical implementation of complex custom ASICs from RTL through tape-out.
The role spans synthesis, place-and-route, timing closure, and signoff while working with design, architecture, and verification teams.
ASIC Implementation Responsibilities
- Run logic and physical synthesis and generate optimized gate-level netlists for timing, area, and power.
- Debug timing, area, and congestion issues with RTL and physical designers.
- Perform RTL- and gate-level power estimation and identify power-reduction opportunities.
- Run formal verification checks between RTL and gate-level netlists and debug failures.
- Perform RTL lint and create waivers with design teams.
- Perform RTL DFT analysis and improve stuck-at fault coverage.
- Develop timing constraints for RTL synthesis and PrimeTime STA at block and SoC top levels.
- Analyze inter-block timing and develop input/output budgets for partition blocks.
- Develop automation scripts and methodologies for front-end tools covering lint, CDC, RDC, synthesis, STA, and power.
- Support design, design verification, and emulation engineers with handoff tasks.
- Provide physical design engineers with timing and congestion feedback.
Minimum Qualifications
- At least 2 years of experience as a front-end synthesis and integration engineer.
- Experience with RTL synthesis and design optimization for power, performance, and area.
- Knowledge of front-end and back-end ASIC tools.
- Experience with RTL design using SystemVerilog or another HDL.
- Experience managing multiple design releases and debugging timing, area, and power issues with cross-functional teams.
- Experience communicating across internal functional teams and vendors.
Preferred Qualifications
- Knowledge of physical design flows such as floorplanning, clock-tree synthesis, and routing.
- Knowledge of STA signoff, including AOCV and POCV.
- Understanding of timing and physical libraries and SRAM memories.
- Experience with EDA tools and Python or TCL scripting.
- Experience with Design Compiler, SpyGlass, PrimeTime, Formality, or equivalent tools.
- Experience with low-power techniques and SoC design integration.
About Meta
Meta builds technologies that help people connect, find communities, and grow businesses.
Compensation varies by skills, qualifications, experience, and location, with possible base hourly, monthly, or annual compensation plus benefits.
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