ASIC Engineer

Role Overview

What You’ll Be Doing

• Develop and deploy methodologies for CDC, RDC, netlist and design auditing, power insertion, lint, and related structural checks.
• Analyze flow results in the context of design intent and identify root causes across RTL, constraints, tools, and methodology.
• Establish quality requirements and readiness criteria while monitoring regressions, violation trends, and sign-off status.
• Collaborate across RTL build, DFT, clocks, reset, low-power, physical-design, verification, and CAD teams.
• Assess tool releases and methodology capabilities and coordinate their integration into project environments.
• Improve runtime, debug efficiency, waiver management, reporting, and training through automation, reusable scripts, and guidelines.

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• 3+ years of experience in ASIC or SoC RTL design or design methodology.
• Practical experience with Verilog or SystemVerilog build, analysis, and debugging.
• Knowledge of digital design and microarchitecture, including pipelines, finite-state machines, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.
• Experience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
• Experience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.

Preferred Qualifications

• Experience with RTL integration, design bring-up, or multi-team debugging at unit, subsystem, chiplet, or SoC level.
• Familiarity with Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor, Power Insertion, or equivalent tools.
• Knowledge of UPF and low-power RTL implementation or verification.
• Experience with SDC, synthesis, static timing analysis, formal verification, or equivalence checking.