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ASIC Engineer, Design Verification

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Key skills for this role

SystemVerilogUVMC

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Experience working across and building relationships with cross-functional design, model and emulation teams
Experience with revision control systems like Mercurial(Hg), Git or SVN
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs

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