{bc}
Apply
company_site

ASIC Engineer, Design Verification

Meta
Bengaluru, IND
Full-time
Entry · 2+ years experience
Onsite
Discovered 3 weeks ago
SystemVerilogUVMCC++System Verilog AssertionsFormal
Free

Job Fit Check

Base Career helps you apply smarter for this job.

?%
Ready to Scan

Key skills for this role

SystemVerilogUVMC
Smart Apply

Full Job Posting

Responsibilities

  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification criteria
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 2+ years of experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification
  • Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation
  • Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications

  • 2+ years experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies
  • 2+ years of experience in development of UVM based verification environments from scratch
  • Experience in ASIC Development life cycles
  • Experience with verification of ARM/RISC-V based sub-systems or SoC (Systems on Chip)
  • Experience working across and building relationships with cross-functional design, model and emulation teams
  • Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs
  • Experience with IP or integration verification of high-speed interfaces like AMBA, PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate), Ethernet
  • Experience with revision control systems like Mercurial, Git or SVN

Apply for this job in 1 click

Skip the repetitive application forms

Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.

Sarah M.James T.Maya R.

Trusted by over 500,000 job seekers on Base Career

Start Free Today

More from this employer

More jobs at Meta

Executive Support Engineer

Sydney, AUS

Discovered TodayFull-time

Security Program Manager, Exam and Audit

London, GBR

Discovered TodayFull-time

Critical Facility Associate

Papillion, USA

Discovered TodayFull-time

Data Center Lead - Houston

Houston, USA

Discovered TodayFull-time

Data Center Lead- PNB

Papillion, USA

Discovered TodayFull-time

Data Center Technician

Papillion, USA

Discovered TodayFull-time

Product Manager, Agent Enablement

London, GBR

Discovered TodayFull-time

Technical Program Manager

Redmond, USA

Discovered TodayFull-time