ASIC Digital Design, Sr Staff Engineer

Role Overview

What You’ll Be Doing

• Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems.
• Build and maintain UVM and SystemVerilog environments integrated with Verilog-A, Verilog-AMS, and mixed-signal simulators.
• Debug analog-digital interface issues, simulation convergence problems, and cross-domain failures.
• Develop assertions, monitors, scoreboards, and automated verification infrastructure.
• Improve AMS simulation efficiency, optimize regression flows, and reduce debug turnaround time.
• Collaborate with analog designers, digital verification engineers, modeling teams, and architecture groups.
• Mentor verification engineers, review test plans and environments, and drive best practices.

Expected Impact

What You’ll Need

• 8+ years of hands-on AMS verification experience and a track record of owning mixed-signal verification sign-off.
• Expert-level SystemVerilog and UVM skills with deep knowledge of testbench architecture and coverage-driven verification.
• Strong working knowledge of Verilog-A and Verilog-AMS for behavioral modeling and mixed-signal simulation.
• Understanding of analog circuit behavior, including bias circuits, regulators, PLLs, ADCs, and DACs.
• Experience with AMS simulators such as Spectre AMS or Xcelium AMS and waveform debug tools.
• Strong scripting skills in Python, Perl, or Tcl for automation and regression infrastructure.
• AI/ML-based verification techniques or automation frameworks are a strong plus.

Working Style

Rewards and Benefits

• The company offers health, wellness, and financial benefits, with additional salary and benefits details provided by the recruiter.