ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore

Leads and designs the building blocks of multiple channels

Applies and drives the design methodology from conception to production

Influences and collaborates with teams to ensure specifications and requirements are met

Interfaces with vendors and design leads on full chip timing closure, PI, and PV

Owns the full electrical planning and specifications of electrical interfaces

Develops multiple solutions, first test vehicles and performs verification and validation

Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan.

Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure,

Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators.

Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.

Scripting skills: Tcl, Python/Perl.

• DFT CAD development – Test Architecture, Methodology and Infrastructure

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