ASIC Design Engineer

About The Role

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.
• Minimum Qualifications
• Education: BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.
• Preferred Qualifications
• Advanced Education: Master’s or PhD in Electrical Engineering with working experiences.
• Experience or coursework in digital logic design, verification methodologies, and protocols (AMBA, PCIe, NAND, DDR)
• Scripting skills (Python, Perl, TCL) and Linux command-line experiences
• Strong problem-solving and communication skills
• Proficiency in AI tool to generate synthesizable and functional RTL code
• COMPENSATION: $110,000/yr - $170,000/yr
• REGARDING COMPENSATION: