ASIC Design Engineer - RTL and Circuits

Collaborate with cross-functional teams to define system-level architecture of mixed-signal chips for power delivery and power management solutions.

Define micro-architecture and specifications of digital IP blocks to improve the power and performance of NVIDIA’s next generation GPUs

Partner with RTL and Design Verification engineers to ensure delivery meets performance and quality expectations.

Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/DFT/LEC/STA)

Partner and work with back-end team until chip tape-out.

Work with firmware teams to define program flow and interface with digital IPs.

Craft and develop behavioral models in RTL for mixed-signal blocks.

B.S. or MS degree in Electrical Engineering (or equivalent experience)

1+ years of proven experience and a background in logic design, Verilog and/or System-Verilog with a deep understanding of physical design and VLSI

Experience with RTL development, Custom Digital Design, and Behavioral Circuit Modeling for mixed-signal blocks.

Well-versed with Verilog/SystemVerilog

Strong familiarity and experience with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis

Strong team player with outstanding interpersonal skills.

Strong knowledge or work experience in Mixed signal and custom designed IPs solutions.

Experience with industry standard communication standards such as JTAG, I2C, SPMI, etc.