AI/ML ASIC Architect

KEY RESPONSIBILITIES

• Responsible for driving the AI/ML ASIC architecture that integrates the AI Storage with GPU/TPU/xPU accelerators, with a particular focus on I/O subsystems connected over UCIe/ PCIe/CXL
• Author architecture specifications in clear and concise language for AI/ML xPU based Accelerator using AI Storage Solutions.
• Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric.
• Create flexible and modular I/O subsystem architectures that can be deployed in either Chiplet, monolithic or 3D form factors.
• Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets.
• Define SoC subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs.
• Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.
• Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap.
• Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.
• LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products.
• Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc
• Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth
• Architect memory-efficient inference/training systems utilizing techniques like pruning, quantization with MX format , continuous batching/chunked prefill, and speculative decoding
• Collaborate with internal and external stakeholders/ML researchers to disseminate results and iterate at rapid pace