"ASIC Engineer, Design for Test" Jobs in United States

ASIC Engineer, Design for Test

Meta · Sunnyvale

Responsibilities Define and implement comprehensive DFT architectures including scan insertion, ATPG, MBIST, LBIST, and boundary scan for large-scale infrastructure ASICs Develop and drive DFT methodology and flows from

Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)

Boeing · El Segundo

Company: Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple Design-for-Test (DFT) Engineers — ASIC Backend to join us as part of our Boeing Electronic Products team at the heart of Boei

ASIC & FPGA Design Engineer Stf - E4

Lockheed Martin ·

Standard Job Description Join Our Team as an ASIC & FPGA Design Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil sp

ASIC Manufacturing Engineer

Nokia ·

ASIC Operations Engineer  Interface with the ASIC design team to deliver ASIC products into production utilizing Outsourced Semiconductor Assembly and Test (OSAT) partner.  Monitor/improve ASIC yields and drive closure

ASIC Manufacturing Engineer

Nokia ·

ASIC Operations Engineer  Interface with the ASIC design team to deliver ASIC products into production utilizing Outsourced Semiconductor Assembly and Test (OSAT) partner.  Monitor/improve ASIC yields and drive closure

ASIC Manufacturing Engineer

Nokia ·

ASIC Operations Engineer  Interface with the ASIC design team to deliver ASIC products into production utilizing Outsourced Semiconductor Assembly and Test (OSAT) partner.  Monitor/improve ASIC yields and drive closure

Member of Technical Staff - Embedded Systems Engineer

Domera Labs · San Francisco

Technology that speaks your language Domera Labs builds Ami, the first AI companion for seniors. Ami brings the power of a smartphone into a more human form: voice-first and deeply personalized We at Domera Labs are reth

ASIC Design Verification Engineer, Digital Signal Processing

Google · Sunnyvale

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applicati

Embedded Systems Engineer II

Nomad GCS · Columbia Falls

This position requires that you must be a US Citizen for consideration and meet all Federal Contractor employee requirements. Nomad GCS does not support the H1B Visa for this position. Nomad GCS is currently seeking a L

About the Role Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working shoulder to shoulder with ou

Emulation Engineer

Cisco · San Jose

Seeking an Emulation Engineer to develop and test complex ASICs for Cisco's advanced networking platforms. Key responsibilities include designing emulation environments and collaborating with cross-functional teams. Idea

AI-Driven ASIC Physical Design Principal Engineer

Cisco · San Jose

We are recruiting a Principal Engineer to drive AI-driven ASIC physical design, collaborating with teams to identify automation targets and benchmark LLM-generated outputs. The role focuses on full development cycles and

ASIC DFT Engineer

Cisco · San Jose

We are looking for an ASIC DFT Engineer to drive hardware design-for-test features and support ATE, in-system test, and diagnostics for next-generation networking chips. Collaborate with RTL and physical design teams, an

ASIC Engineer

Cisco · San Jose

Join us as an ASIC Engineer to drive qualification, reliability, and RMA testing for advanced Silicon One ASIC products. Collaborate with cross-functional teams to enhance test coverage and resolve complex engineering ch

Senior ASIC Engineer

Cisco · San Jose

We are recruiting a ASIC Engineer to define, design, and verify ASIC and subsystems for Cisco platforms. You will contribute to multi-disciplined engineering teams, develop reusable code, and lead design and verification