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"Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)" Jobs in India
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Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
Erbity Private Limited · Bengaluru
MidFull-timeHybrid
If breaking designs before tapeout sounds fun, you’re exactly who this is for. 4–6 years in IP/Block/Subsystem verification Strong expertise in SystemVerilog and UVM methodology Experience building test plans, environmen
Skills
SystemVerilogUVMAXIAHB
Discovered 3 weeks ago
ApplyDesign Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
Erbity Private Limited · Hyderabad
MidFull-timeHybrid
If breaking designs before tapeout sounds fun, you’re exactly who this is for. 4–6 years in IP/Block/Subsystem verification Strong expertise in SystemVerilog and UVM methodology Experience building test plans, environmen
Skills
SystemVerilogUVMAXIAHB
Discovered 3 weeks ago
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