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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco - Pune

Discovered 3 weeks ago

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

CiscoPune, INDFull-timeSeniorOnsiteDiscovered 3 weeks ago

VerilogUVMPythonCRTL designLinux

Full page Apply

What You'll Do We are looking for talented and experienced Design Verification Engineer to join our team and be a hands-on verification engineer for Cisco's silicon photonics driver integrated circuits for next generati

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco · Pune

SeniorFull-timeOnsite

Skills

VerilogUVMPythonC

Discovered 3 weeks ago

Apply

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