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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

Cisco - Pune

Discovered 3 weeks ago

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

CiscoPune, INDFull-timeSeniorOnsiteDiscovered 3 weeks ago

SystemVerilogPythonCUVMRTLFPGA

Full page Apply

Meet the Team Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

Cisco · Pune

SeniorFull-timeOnsite

Skills

SystemVerilogPythonCUVM

Discovered 3 weeks ago

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