"ASIC Design Verification Engineer" Jobs in India

ASIC Design Verification Engineer

CHIPLOGIC TECH · Bengaluru

ASIC Design Verification Engineer Published 10 months ago Description We are looking for a skilled ASIC Design Verification Engineer to join CHIPLOGIC TECH's dynamic team in Bengaluru. As an ASIC Design Verification E

Senior ASIC Design Verification Engineer

Hewlett Packard Enterprise · Bengaluru

Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live,

Senior ASIC Design Verification Engineer

Hpe · Bengaluru

Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live,

Senior ASIC Design Verification Engineer

Hpe · Bengaluru

Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live,

ASIC Design Verification Engineer | UVM | Exp. 8+ years

Cisco · Bengaluru

You will contribute to developing Cisco’s progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware

ASIC Design Verification Engineer

Cisco · Bengaluru

Meet the Team: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service

ASIC Design Verification Engineer | UVM | Exp 8+ Years

Cisco · Bengaluru

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, doc

Senior Staff ASIC Design Verification Engineer

MaxLinear, Inc. · Bengaluru

We are looking for a Senior Staff ASIC Design Verification Engineer to lead complex verification execution and contribute significantly to IP, Subsystem, and SoC-level verification. This role requires strong hands-on exp

Principal ASIC Design Verification Engineer

MaxLinear, Inc. · Bengaluru

We are seeking a Principal ASIC Design Verification Engineer to provide technical leadership and strategic direction across IP, Subsystem, and SoC verification. This role is ideal for a verification architect and technic

ASIC Digital Design Verification Engineer

Vitesco Technologies GmbH · Bengaluru

Schaeffler is a dynamic global technology company and its success has been a result of its entrepreneurial spirit and long history of private ownership. Does that sound interesting to you? As a partner to all of the majo

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

Cisco · Pune

Meet the Team Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco · Pune

What You'll Do We are looking for talented and experienced Design Verification Engineer to join our team and be a hands-on verification engineer for Cisco's silicon photonics driver integrated circuits for next generati

ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years

Cisco · Bengaluru

Meet the Team Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in

Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)

Erbity Private Limited · Bengaluru

If breaking designs before tapeout sounds fun, you’re exactly who this is for. 4–6 years in IP/Block/Subsystem verification Strong expertise in SystemVerilog and UVM methodology Experience building test plans, environmen

Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)

Erbity Private Limited · Hyderabad

If breaking designs before tapeout sounds fun, you’re exactly who this is for. 4–6 years in IP/Block/Subsystem verification Strong expertise in SystemVerilog and UVM methodology Experience building test plans, environmen