Wafer Process Engineer (IRSP) 2nd Shift

The position will primarily focus on learning and supporting wafer processing steps required to further develop and build IR emitter pixels for the IRSP program area. This includes thin film deposition by PVD, photoreist coats, photoresist develops, dry etches (RIE and ion mill), descums, ultrasonic (US) resist strips, immersion wet etches, microscope inspections, and thin film metrology. The successful candidate will need to develop an understanding of relevant process integration dependencies (e,g. interaction of patterned resist with etch processes). Understanding the importance of processing results and the need for supporting program schedules is critical. As time permits, a secondary goal is to become familiar with the process flows required to fabricate advanced interconnects on passive and/or active device wafers (e.g. through-Si Vias (TSV), flip-chip bumps, Cu pillars, redistribution layers, high density microbumps, and Si interposers). This position will support both externally and internally funded projects.