Verification Hardware Engineer

Job Area:

Key Responsibilities

• Develop and implement test benches using SystemVerilog and UVM .
• Design and execute verification plans based on design specifications and architecture documents.
• Apply Object-Oriented Design (OOD) principles to build scalable and reusable verification components.
• Collaborate with cross-functional teams to define test strategies and ensure comprehensive coverage.
• Write and maintain scripts (Python, Perl, Shell, etc.) to automate verification flows and improve productivity.
• Debug and resolve complex issues in simulation and emulation environments.
• Contribute to the development of verification infrastructure and methodologies.
• Communicate effectively with team members and stakeholders to report progress, issues, and solutions.

Required Skills and Qualifications

• Proficiency in SystemVerilog and UVM methodology.
• Strong understanding of Object-Oriented Programming (OOP) and test bench architecture .
• Experience with scripting languages such as Python, Perl, or Shell.
• Solid grasp of computer architecture and digital design fundamentals.
• Demonstrated problem-solving skills and the ability to work independently.
• Excellent communication skills , both written and verbal.