Verification Engineer

We look for engineers with the following mindset

Required skills and experience

• Strong software skills Python preferred, other languages acceptable
• Python preferred, other languages acceptable
• Understanding of digital hardware concepts Ability to read and debug RTL in SystemVerilog Familiarity with debugging waveforms
• Ability to read and debug RTL in SystemVerilog
• Familiarity with debugging waveforms

Desirable skills and experience

• Pre-silicon RTL verification Verification planning and execution from specification Building testbenches Stimulus creation Functional modelling of hardware blocks Checker creation Coverage definition/closure
• Verification planning and execution from specification
• Building testbenches
• Stimulus creation
• Functional modelling of hardware blocks
• Checker creation
• Coverage definition/closure
• Transaction-Level Modelling Whether in UVM, SystemC or another methodology
• Whether in UVM, SystemC or another methodology
• SystemVerilog Assertions (SVA)
• Software fluency in multiple languages