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USB and System Level Verification Lead
MediaTek
Bengaluru, IND
Full-time
Senior · 12+ years experience
Onsite
Discovered 3 weeks ago
SystemVerilogUVM
Free
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SystemVerilogUVM
Role Overview
As a Design Verification Lead at MediaTek, you will play a critical role in ensuring the quality and reliability of our high speed IO’s in all our cutting-edge SoC designs.
You will work on innovative projects that power the future of technology, collaborating with a global team of experts in a fast-paced and dynamic environment.
You will lead our high-speed IO verification efforts across designs and ensuring quality verification with coverage closure.
The candidate should have a strong background in RTL verification at IP/Sub System or SoC verification and related methodologies and flows.
Background in USB verification at IP or Sub System level is needed.
Key Skills for This Role
SystemVerilogUVM
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Job Description
As a Design Verification Lead at MediaTek, you will play a critical role in ensuring the quality and reliability of our high speed IO’s in all our cutting-edge SoC designs. You will work on innovative projects that power the future of technology, collaborating with a global team of experts in a fast-paced and dynamic environment. You will lead our high-speed IO verification efforts across designs and ensuring quality verification with coverage closure. The candidate should have a strong background in RTL verification at IP/Sub System or SoC verification and related methodologies and flows. Background in USB verification at IP or Sub System level is needed. Experience on System level validation aspects is highly desirable. Low power verification exposure is desirable. Experience in test planning & testbench design/improvements and coverage closure is needed. Experience in leading high performing teams is desirable.
Main Requirements and Qualifications
- Key Responsibilities:
- Drive the development and implementation of comprehensive verification test plans for high-speed IO IPs at IP/Subsystem and SoC level.
- Build and enhance testbenches for new Sub Systems, develop verification flows and test cases using System Verilog and UVM methodology.
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