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The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip.
DCS has a broad portfolio of products widely deployed by the industry’s cutting-edge server/storage OEMs and hyperscale datacenters.
Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age.
Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers.
Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership.
An opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products.
This will involve taking a design from initial concept through to production.
Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices.
Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter.
Microchip fosters continuous learning in a challenging and rewarding environment.
If this sounds like the kind of environment you'd like to participate in, we'd like to hear from you!
As a Staff Design Engineer, your job will entail the following:
• Own design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.
• Develop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.
• Generate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams.
• Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.
• Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.
• Support Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements.
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The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry’s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership.
An opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment you'd like to participate in, we'd like to hear from you!
As a Staff Design Engineer, your job will entail the following:
Own design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.
Develop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.
Generate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams.
Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.
Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.
Support Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements.
To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
A leading provider of smart, connected, and secure embedded control solutions.
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Senior · 12+ years experience
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