Technical Lead Manager, Machine Learning, Memory Subsystem Design

Responsibilities

• Lead, mentor and manage a team of RTL Design and DV Engineers developing DRAM subsystems including HBM.
• Collaborate closely with the cross-functional teams (e.g. Design for Test, Signal/Power Integrity, Packaging, Physical Design,Software, Silicon Validation, Silicon Engineering) to plan and execute throughout the development cycle.
• Interface with third party IP providers of memory related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects.
• Interface with DRAM manufacturers during the design and validation of DRAM subsystems.
• Drive improvements in design methodologies, processes, and quality control measures.
• - Lead, mentor and manage a team of RTL Design and DV Engineers developing DRAM subsystems including HBM. - Collaborate closely with the cross-functional teams (e.g. Design for Test, Signal/Power Integrity, Packaging, Physical Design,Software, Silicon Validation, Silicon Engineering) to plan and execute throughout the development cycle. - Interface with third party IP providers of memory related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects. - Interface with DRAM manufacturers during the design and validation of DRAM subsystems. - Drive improvements in design methodologies, processes, and quality control measures.

Minimum qualifications:

Preferred qualifications: