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General Summary:
System SI/PI owner across full platform (SoC ↔ package ↔ board ↔ connectors ↔ external systems)
Technical owner for high-speed interfaces and system margins
Cross-functional leader driving SIPI driven design convergence across silicon, package, and platform teams
Own end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)
Define design targets and layout design guidelines for all high-speed interfaces
Influence architecture decisions early in product lifecycle
Ensure SI/PI alignment with product KPIs (performance, yield, power, cost)
Drive new IP co-design across IC/IO/PHY, package, and PCB
Ensure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)
Influence PDN architecture definition at system and package level, provide related optimum cost solutions
Ensure cross functional alignments. Partner with SoC/PHY design teams, Package engineering, Board/system teams and OEM/ODM ecosystem
Lead design reviews and signoff decisions
Represent SI/PI in program reviews and leadership forums
Define company-wide SI/PI methodologies
Drive correlation between pre-silicon models and silicon/lab data
Lead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions
Drive best practices adoption across programs
Establish golden methods for system SI/PI
Mentor senior engineers across SI/PI domains
Memory: LPDDR4/5/6
High-speed IO: PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs
Camera/Display: MIPI CSI/DSI
System PDN
12+ years in Signal Integrity / Power Integrity / High-speed systems
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Proven ownership of multiple tapeouts or high-volume products
Experience with: Packaging technologies like FCBGA, 2.5D/3D; Products like Data center, Compute and Servers
Track record of Patents, standards contributions, or published work internal / external conferences
Minimum Qualifications:
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Full-time
Senior · 12+ years experience
Onsite
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