Staff Engineer Verification

• create and define verification plans
• develop verification environments for our ICs using Universal Verification Methodology (UVM)
• draw on test scenarios using System Verilog
• verify functionality using the Constrained Random approach
• develop assertions in System Verilog for formal verification
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies
• provide proactive support to users of our verification flow environment
• be responsible for our verification methods
• You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline
• You have at least 3 years of experience in Metric Driven Verification(digital and/or mixed-signal)
• You have capabilities and experience in working with microcontroller-based ICs, as well as security and safety requirements;
• You have excellent know-how with UVM especially using System Verilog
• Have knowledge of firmware and RTL design (VHDL/Verilog)
• Ideally have knowledge of Cadence verification software

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